1. Field of the Invention
The present invention relates to a digital filter using an finite impulse response ("FIR") filter which processes signals by product sum operation, more particularly, it relates to a decimation type digital filter which operates at the input signal period t1 and output signal period t2 (t1&lt;t2) to generate the M number of output signals (M=N.multidot.t1/t2) by the N number of input signals (N=1, 2, 3, . . . ).
2. Description of Related Art
Since a digital filter indicates the signal in digital values and processes it by a digital circuit, a good accuracy and stability can be obtained, thereby constituting a filter of characteristics which is difficult to be realized by an analog filter.
First, citing a direct FIR filter, hereinafter referred to as FIR (Finite Impulse Response) filter, called a transversal filter stated on Pages 113 to 118 in "Digital Signal Processing System, Digital Technology Series 3", issued by Tokai University Printing Association as an example, a conventional digital filter will be described with reference to the drawings.
The FIR filter described above will be first represented by a formula. The N-tap FIR filter is represented as ##EQU1##
where, input signal x[n], output signal y[n] and filter coefficient h[i] (i=0 to N-1). FIG. 1 is a block diagram based upon the figure shown on Page 117 of the aforesaid literature for the essential configuration by a 1-multiplier 1-adder type hardware of the FIR filter of the aforesaid formula. The conventional example will be explained with reference to the block diagram.
In the figure, the numeral 100 is an N-1 step shift registers for the input signal, and to the first step of which a multiplexer 101 is connected to select whether to make data to be inputted the input signal x(n) or the data from the last step of the shift register 100.
The numeral 102 indicates an N-word-coefficient ROM for storing a filter coefficient h[i] of the above formula (1), in which address ranges obtainable within 0 to N-1 correspond exactly to the obtainable ranges of an index i of the filter coefficient h[i].
The address add of the coefficient ROM 102 is designated by an address register 103 and the filter coefficient h[i] stored in the designated address add is inputted to a multiplier 104, and multiplied by the input signal x[n-i] from the utmost end of the shift register 100 therein.
Multiple result data h[i].multidot.x[n-1] from the multiplier 104 is given to one end of an adder 105 and added to data of an accumulation register 106, in which it is stored again.
Next, the operation of the conventional FIR filter constructed as aforementioned will be described according to a flow chart shown in FIG. 2.
First, in Step #1, the accumulation register 106 is reset (R.rarw.0) by the reset signal RST, N-1 is written into the address register 103 of the coefficient ROM 102 (add .rarw.N-1) and N-1 is substituted in a dummy variable i (i.rarw.N-1). Here, the dummy variable corresponds to a control register not shown.
Then, in Step #2, product sum operation is conducted by using the multiplier 104 and the adder 105 (R.rarw.R+h[i].multidot.x[n-i], that is ##EQU2##
In Step #3, the multiplexer 101 is controlled such that x[n] is inputted to the shift register 100, whose content is shifted rightward by one step. Also, the address add and the dummy variable i are decremented (add.rarw.add-1, i.rarw.i-1).
Then, in Step #4, product sum operation is conducted by using the multiplier 104 and the adder 105 (R.rarw.R+[i].multidot.x[n-i], that is ##EQU3## is obtained when the operation is repeated till i=0). After completing the product sum operation, in Step #5, the multiplexer 101 is controlled such that the right end output of the shift register 100 is inputted to its left end, and the content of the shift register 100 is shifted rightward by one step. The address add and the dummy variable i are also decremented (add.rarw.add-1, i.rarw.i-1). Then, in Step #6, it is determined whether the dummy variable i is smaller than zero. When it is zero or larger than zero, the procedure returns to Step #4 and when smaller than zero it proceeds to Step #7. That is, Steps #4, #5 are repeated until i becomes 0. When the product sum operation is finished, since the content of the accumulation register 106 is y[n] defined by the formula (1) in Step #7, it is outputted and the procedure returns to Step #1 for operation of the output signal y[n+1] of the next time point.
The FIR filtering is executed by the aforesaid operation.
Next, a decimation filter whose output signal is the thinned out output signal of the above FIR filter will be explained. The decimation filter is designed to thin out the output signal and used for realizing the filter such as a low-pass filter which eliminates the high frequency component. In the following, the conventional N-tap decimation filter which operates at the input signal period t1 and the output signal period t2 (t1&lt;t2), generates the output signal by N number of input signals (N=1, 2, 3, . . . ) and outputs the output signal y[N] corresponding to data till the input signal x(N) during the period t2 will be explained as an example.
When applying to the operation of the aforesaid FIR filter, it may be operated in such a way that the output signal y[N] corresponding to the data till the input signal x[N] is outputted during the K (=t2/t1, K is an integer) number of input signals, and the output signal corresponding to data from the input signals x[n+1] to x[N+K-1] becomes y[N]. That is, it is same as thinning out the output signal corresponding to the data from the input signals x[n+1] to x[n+K-1 ].
Such a decimation filter may be expressed by the following formula. (T is an integer) ##EQU4##
FIG. 3 is a block diagram showing the configuration of a conventional decimation filter using the FIR filter. In the figure, the numeral 200 designates a control circuit which controls whether or not to latch product sum operation results outputted from the adder 105 stored in the accumulation register 106 in a latch 107. When the data are processed at every K number as the aforesaid formula, the control circuit 200 controls such that the latch 107 latches the holding value of the accumulation register 106 after the K number of input signals are inputted to the shift register 100 after filtering once.
In the foregoing configuration of the decimation filter, irrespective of the output signal being thinned out, the product sum operation must be completed till sampling the next input signal, so that the product sum operation must be effected at the same operation speed as the FIR filter aforementioned. That is, the product sum operation must be conducted N times during one sampling period (=one input signal period).
Therefore, as shown by the broken line in FIG. 11, the control circuit 200 may be constructed to control the coefficient ROM 102, multiplier 104 and adder 105 by its control signal in the same way as the latch 107 and control such that the coefficient ROM 102, multiplier 104, adder 105 and latch 107 operate only when generating the output signal and not operate while the output signal is thinned out.
Also in this case, however, since the product sum operation necessary for the filtering must be effected during the input signal period t1 between one input signal and the next input signal in the decimation filter, the operating speed of the product sum operation is same as that when the output signal is not thinned out, thus elements such as a multiplier and an adder which operate at the same speed are required. Also, in the hardware side, since each of the input signals must be held during the output signal period t2, a shift register having taps of N-1 steps is required.
As an example, the configuration and operating speed of a decimation filter having the number of taps N=128 and output signal period/input signal period =K=t2/t1 will be considered. In the above configuration, a shift register of 127 steps is needed as a hardware and the operating speed of input signal period t1.times.128 is required in the coefficient ROM 102, multiplier 104, adder 105 and accumulation register 106 as the operating speed.
As such, in the conventional digital filter, even when the output signal period is longer than the input signal period, since the shift register is used as storing means to hold respective input signals during the output signal period, the storing means having the same capacity as the digital filter in which two periods are same is needed, thus such a problem is encountered that the construction of the hardware becomes complicated and its capacity can not be optimized.
Likewise, since filtering for the output signal or the product sum operation by the number of taps must be effected in the input signal period t1 of one data, a high speed arithmetic unit is required, thus a filtering circuit is difficult to design and power consumption becomes higher.